## Linearity Improvement Techniques

Linearity Improvement Techniques for on-chip Amplifiers The Fantastic Four of Linearity Improvement Techniques Linearity is one of the most, if not THE most, important metric in circuit design. All analog circuits are inherently non-linear mainly because of non-linear behavior of transistors. Many linearity improvement techniques have been discovered or invented in literature yet we only […]

## ACLR Simulation in Cadence

ACLR Simulation in Cadence with MultiTones Envelope transient (ET) is a usual method to simulate ACLR with modulated input signals aka waveforms. We simulate circuit performance with same waveforms (little wishful) that we are going to transmit, and whatever ACLR comes out of that, that is it, we optimize ACLR directly with given waveforms. However, […]

## Ideal Blocks in Cadence

Ideal Blocks in Cadence Time to time, debugging or modelling a circuit, we look for ideal blocks in Cadence that can do the job, prove the concept before you go on fully developing the thing. We heard you. Here are some ideal blocks that are already available in Cadence Virtuoso libraries that you can get […]

## Loadline Design

Loadline Design The output of a power amplifier (PA) is terminated with a specific impedance. This impedance is required for optimal linearity or power generation or efficiency or combination of such specs, and is determined by loadpull analysis. We call it loadline. While a loadline helps PA deliver its performance, the matching (VSWR) gets ruined […]

## IQ Calibration

TX RSB Improvement by IQ Calibration Residual sideband suppression (RSB) is one of key TX specs. We want to minimize this because this degrades EVM (when LO is centered to CC leading to signal and its image falling on top of each other) or degrades ACLR (when LO is not centered to CC leading to different signal […]

## LO Leakage in TX

LO Leakage in TX LO leakage suppression is one of key TX specs. We want to minimize this because this is just like another distortion to your signal which either degrades EVM if LO is parked at the center of signal or degrades ACLR if LO is parked sideways. There are four main ways LO […]

## Impedance Matching and Quality Factor

A Journey from Resonance to Impedance Matching Chp. 7: Quality Factor and Impedance Matching One Must Not Tell Lies. We have reached the finale of this saga. We have discussed how quality factor of a resonator led to signal gain and how did RF designers used that gain to boost impedance. Today we will look […]

## Quality Factor and Bandwidth

A Journey from Resonance to Impedance Matching Chp. 6: Quality Factor and Bandwidth Q-factor is Inverse of 3dB BW. Design or Coincidence? You have seen this $$ Q = frac{1}{FBW}$$ where FBW is fractional bandwidth (dfrac{Delta omega}{omega_o}) and (Delta omega) represents 3dB bandwidth around your resonance frequency (omega_o). We tried looking this up on internet […]

## Transient response of LC Tank

A Journey from Resonance to Impedance Matching Chp. 5: Quality Factor and LC Tank Behavior in Time Domain To develop further intuition in Q-factor and extend its application to matching and bandwidth, it is prudent to study time domain behavior of LC tank. We show how an LC tank starts up, how the voltage developed […]

## Series to Parallel Conversion – Intuition

A Journey from Resonance to Impedance Matching Chp. 4: Series to Parallel Conversion using Quality Factor The Underrated Magic Trick A series impedance can be transformed to equivalent parallel impedance and vice versa. This is the most underrated trick yet it is fundamental to matching network design. Math behind series to parallel conversion is simple. […]