RFIC Design


LO Leakage in TX

LO leakage suppression is one of key TX specs. We want to minimize this because this is just like another distortion to your signal which either degrades EVM if LO is parked at the center of signal or degrades ACLR if LO is parked sideways.

There are four main ways LO leaks in a TX:

  1. DC offset: A mixer has two frequencies going in, \(f_{bb}\) and \(f_{lo}\), and ideally one frequency coming out, \(f_{lo}+f_{bb}\). If \(f_{bb}=0\) (i.e, DC), your mixer spits out \(f_{lo}\). Now your TX is most likely differential so this DC-upconverted \(f_{lo}\) will cancel out being common mode. However, if there is an offset in DC (meaning +ive side carrying little different DC bias than -ive side say because of mismatch), you will have some \(f_{lo}\) leakage. This is the main phenomena for LO leakage in Active Mixer based TX which are carrying currents, and mismatch in currents are easy to come by. This is sometimes referred to as carrier suppression (CARSUP) in industry. You can measure DC currents of +ive and -ive side, calibrate them to be equal and this kind of LO leakage will be gone.

  2. LO feedthrough: An LO signal present at the gate of transistor couples to drain or source terminals by parasitic \(C_{GS}\) and \(C_{GD}\) capacitances, and leaks to the output. We make mixers double-balanced to cancel this LO leakage. There is still some residual LO leakage due to mismatches, however this is non-dominant. We call this method of LO leakage as LO feedthrough (LOFT). You can calibrate this out by intentionally creating a DC offset based LO leakage such that CARSUP and LOFT are out of phase and cancel.

  3. 2\(f_{lo}\) downconversion: This is a rather less known phenomena and topic of discussion in this article. Source node of mixer switching devices is rich with 2\(f_{lo}\) and its harmonics. These mix with \(f_{lo}\) and land back at \(f_{lo}\) itself creating LO leakage. Debug and details of it are presented below.

  4. Coupling: LO can directly couple to TX port on chip or on package or on PCB if LO and TX routings are running nearby. This is a non-dominant source of leakage as routings are extensively EM simulated and couplings are already mitigated at design level unless you miss something.

LO Leakage Debug

1.1 Background

LO leakage was observed at TX output which was ~35dBc at 3.5GHz even when DC offset was calibrated out. The cause of LO leakage was just 20pH inductance mismatch in TX which created 35dBc LO leakage levels. Barebones schematic of our TX is shown below. Baseband signals are received at GM cell which converts them to currents, and these currents are then passed through switching core which upconverts them to RF frequency (this is a typical Gilbert cell mixer).

tx schematic

1.2 Short Story

LO leakage was created by inductance mismatch at source node of mixer. This node is rich with even harmonics of LO, a slight mismatch in +ive & -ive impedance at this node results in sizeable differential even harmonic currents which mix with odd harmonics of LO to land back at LO leakage in phase. LOL created by each even harmonic itself is tiny, but they add up and amount to significant LO leakage.

downconversion of 2flo produces lo leakage

1.3 2\(f_{lo}\) Dips at Mixer Source Node

The mixer switch node has 2\(f_{lo}\) dips which result from tug of war between +ive and -ive transistor of mixers during LO transition. Source node follows gate. Say LO+ is high, MX+ transistor is ON, source node is following LO+. As LO+ dips, source node also goes down. However, LO- would be rising and MX- would start to turn ON and gain control of source node. Therefore, right at middle point of transition, source node stops following LO+ as MX+ has turned OFF and starts following LO- as MX- is turned ON. This brings the dip back up. This is the origin of dip. Since LO transitions happen twice a cycle, we find these dips appearing twice LO frequency.

dips at mixer source node

1.4 Not Just 2\(f_{lo}\) – 4,6,8\(f_{lo}\),… all of them

Although the dips repeat every 2\(f_{lo}\), they contain significant energy at all of their harmonics. This makes sense mathematically because smaller they duty cycle of a pulse, the similar the energy level its harmonics will have to the limit that an ideal impulse consist of infinite harmonics all with equal amplitude.

cadence simulation of active mixer showing dips at source node

1.5 Even Harms Mix with Odd Harms to create LO Leakage – The Math

The Fourier series of an ideal square wave consists of odd harmonics of LO. The third harmonic is 3 times lower in magnitude, 5th is 5 times lower and so on…

$$V_{LO}=\ \frac{4}{\pi}\left[sin(\omega_{LO}t)+\frac{sin(3\omega_{LO}t)}{3}+\frac{sin(5\omega_{LO}t)}{5}+\frac{sin(7\omega_{LO}t)}{7}+..\right]$$

The 2\(f_{lo}\) dips at mixer source node consists of all harmonics of 2LO with similar energy levels at all harmonics.

$$V_{DIP}=a_{DIP}.cos\left({2\omega}_{LO}t\right)+\ b_{DIP}.cos\left({4\omega}_{LO}t\right)+c_{DIP}.cos\left({6\omega}_{LO}t\right)+d_{DIP}.cos({8\omega}_{LO}t)+.. $$

where aDIP, bDIP,.. are Fourier series coefficients.
Plots below shows VLO and VDIP plotted, more of a sanity check, that Fourier series is computed right, they do add up to make the signal we want.

The impedance at mixer source node is almost capacitive, therefore the current drawn through the mixer to that capacitance leads the VLO by 90 degrees. We can write the current as:
$$I_{DIP}=\ \frac{A_{DIP}}{Z_{n\omega}}\left[cos({2\omega}_{LO}t+\frac{\pi}{2})+\ cos({4\omega}_{LO}t+\frac{\pi}{2})+cos({6\omega}_{LO}t+\frac{\pi}{2})+cos({8\omega}_{LO}t+\frac{\pi}{2})+..\right]$$ $$I_{DIP}=\ \frac{{-A}_{DIP}}{Z_{n\omega}}\left[sin({2\omega}_{LO}t)+\ sin({4\omega}_{LO}t)+sin({6\omega}_{LO}t)+sin({8\omega}_{LO}t)+..\right] $$

where Zn\(\omega\) is the impedance looking downwards at source node of mixer at corresponding frequency. This current can be treated similarly as baseband signal current that means it mixes with LO signal and gets upconverted.

current flow of signal and 2flos in active mixer

Table below shows some of examples of different combinations of even harmonics at mixer input (source node) mixing with LO harmonics (at gate node) and creating LO leakage (LSB column).

\[ \begin{array}{|l|c|c|c|l|} \hline \text{MIXER IN} & \text{LO}& I_{MXOUT} = V_{LO}\times VI_{DIP}&USB&LSB \\ \hline \omega_{BB}& \omega_{LO} & A_{bb}\;sin(\omega_{BB}\;t) \times \dfrac{4}{\pi}sin(\omega_{LO}\;t) & \dfrac{2}{\pi} cos(\omega_{LO}+\omega_{BB})t &\dfrac{2}{\pi} cos(\omega_{LO}-\omega_{BB})t\\ \hline 2\omega_{LO}& \omega_{LO} & \dfrac{-a_{DIP}}{Z_{2\omega}} sin(2\omega_{LO}\;t) \times \dfrac{4}{\pi}sin(\omega_{LO}\;t) & \dfrac{2}{\pi} \dfrac{-a_{DIP}}{Z_{2\omega}} cos(3\omega_{LO}\;t) &\dfrac{2}{\pi} \dfrac{-a_{DIP}}{Z_{2\omega}} cos(\omega_{LO}\;t)\\ \hline 2\omega_{LO}& 3\omega_{LO} & \dfrac{-a_{DIP}}{Z_{2\omega}} sin(2\omega_{LO}\;t) \times \dfrac{4}{\pi}\dfrac{sin(3\omega_{LO}\;t)}{3} & \dfrac{2}{3\pi} \dfrac{-a_{DIP}}{Z_{2\omega}} cos(5\omega_{LO}\;t) &\dfrac{2}{3\pi} \dfrac{-a_{DIP}}{Z_{2\omega}} cos(\omega_{LO}\;t)\\ \hline 4\omega_{LO}& 3\omega_{LO} & \dfrac{-b_{DIP}}{Z_{4\omega}} sin(4\omega_{LO}\;t) \times \dfrac{4}{\pi}\dfrac{sin(3\omega_{LO}\;t)}{3} & \dfrac{2}{5\pi} \dfrac{-b_{DIP}}{Z_{4\omega}} cos(7\omega_{LO}\;t) &\dfrac{2}{5\pi} \dfrac{-b_{DIP}}{Z_{4\omega}} cos(\omega_{LO}\;t)\\ \hline 4\omega_{LO}& 5\omega_{LO} & \dfrac{-b_{DIP}}{Z_{4\omega}} sin(4\omega_{LO}\;t) \times \dfrac{4}{\pi}\dfrac{sin(5\omega_{LO}\;t)}{3} & \dfrac{2}{5\pi} \dfrac{-b_{DIP}}{Z_{4\omega}} cos(9\omega_{LO}\;t) &\dfrac{2}{5\pi} \dfrac{-b_{DIP}}{Z_{4\omega}} cos(\omega_{LO}\;t)\\ \hline 6\omega_{LO}& 5\omega_{LO} & \dfrac{-c_{DIP}}{Z_{6\omega}} sin(6\omega_{LO}\;t) \times \dfrac{4}{\pi}\dfrac{sin(5\omega_{LO}\;t)}{5} & \dfrac{2}{7\pi} \dfrac{-b_{DIP}}{Z_{6\omega}} cos(11\omega_{LO}\;t) &\dfrac{2}{7\pi} \dfrac{-v_{DIP}}{Z_{6\omega}} cos(\omega_{LO}\;t)\\ \hline \end{array} \]
Table above draws two important learnings:

  1. All even harmonics of LO mix with odd harmonics of LO and land back at LO in phase. Although each might be contributing a tiny amount, their sum can be significant.

  2. LOL coming from mixing of higher harmonics does not die away fast – LO odd harmonic amplitude decreases, VDIP Fourier coefficients decrease but Zn\(\omega\) also decreases balancing out.
Corollary: An interesting point to also note is that if mixer source node did not have imaginary parasitic, say just resistive load, mixer current would not be 90 deg out of phase with voltage, that means when you mix VLO and VDIP now, LOs wont land back in phase and we wouldn’t have this issue (LO leakage will be tiny).

1.6 Implications of Higher Harmonics at Play

Implication of all the higher harmonics (2,4,6,8\(f_{lo}\)..) adding to LO leakage is that now mixer source node is very sensitive to impedance mismatch between +ive and ive.

Figure below shows layout of our routings connecting GM and Mixer. We did not EM simulate them, and sufficed with parasitic RC extraction thinking that this is still baseband domain, how would parasitic inductance extraction benefit us. Our circuits already take long enough to simulate, so we are always prudently cutting down on EM models to make sims faster and this seemed like a wise choice. Little did we know that this would get us. When EM simulated, these routings showed 20pH inductance difference between +ive and -ive routing. 

routing mismatch

This 20pH difference – although appears small – wreaks havoc. Let’s model the circuit as shown below. We have ~200fF parasitic cap at mixer source node. We add 45pH in series to +ive side and 25pH to -ive side. We see that at lower frequency say 2\(f_{lo}\), this 20pH creates a small impedance delta. However, as we move to higher and higher frequencies, the impedance difference between +ive & -ive grows relatively much bigger. This creates significant differential currents which then flow through mixer and mix with odd harmonics of LO – thus creating LO leakage.

mismatch in routing creates lo leakage
Table shown below calculates LOL contribution of each harmonic. VDIP rms is the Fourier series coefficients or voltage amplitude of corresponding frequencies. VDIP data was taken from simulation of simplified mixer bench. We show that this VDIP across impedance differential created by 20pH produces current through mixer, which go through mixer conversion gain and come out tiny uA levels creating about -50dBc LO leakage individually. However, when added they start reaching -30, -40 dBc level quickly. We added upto 10 harmonics which gave -40dBc LOL. Addition of more harmonics will degrade it further until one point where harmonic is at such a high frequency that VDIP for that harmonic will be miniscule and mixer conversion gain would have dropped a lot. This game would stop there, and that will be the final LOL, no more additions.
\[ \begin{array}{|l|c|c|c|c|c|c|l|} \hline \text{ } & \text{Freq Hz}& \text{ }&\text{ }&\text{Idiff uArms}&\text{Mixer Gain}&\text{I MX OUT uArms} & \text{ }\\ \hline f_{bb}& 9.5M&\text{ }&\text{ }&2900&\dfrac{2}{\pi}&1846\\ \hline \text{ } & \text{Freq Hz}& \text{ }&\text{Gdiff mho}&\text{Idiff uArms}&\text{Mixer Gain}&\text{I MX OUT uArms}&\text{LOL dBc} \\ \hline 2f_{lo}&7G&20&7.88 \times 10^{-6}&0.2&\dfrac{2}{\pi}\left[1+\dfrac{1}{3}\right]&0.1&\textcolor{#40CE7F}{-82.8}\\ \hline 4f_{lo}&14G&16&5.89 \times 10^{-4}&9.4&\dfrac{2}{\pi}\left[\dfrac{1}{3}+\dfrac{1}{5}\right]&3.2&\textcolor{#FEDB39}{-55.2}\\ \hline 6f_{lo}&21G&11&2.35 \times 10^{-3}&25.8&\dfrac{2}{\pi}\left[\dfrac{1}{5}+\dfrac{1}{7}\right]&5.6&\textcolor{#E91E56}{-50.3}\\ \hline 8f_{lo}&28G&4.2&8.78 \times 10^{-3}&36.9&\dfrac{2}{\pi}\left[\dfrac{1}{7}+\dfrac{1}{9}\right]&6&\textcolor{#E91E56}{-49.8}\\ \hline 10f_{lo}&35G&0.9&2 \times 10^{-8}&18&\dfrac{2}{\pi}\left[\dfrac{1}{9}+\dfrac{1}{11}\right]&2.3&\textcolor{#FEDB39}{-58.3}\\ \hline \text{ }&\text{ }&\text{ }&\text{ }&\text{ }&\text{ }&Total&\textcolor{#E74C3C}{-40.6}\\ \hline \end{array} \]

1.7 20pH Mismatch – Cause and Cure

Figure below shows how did we get 20pH mismatch in layout. We have big GM transistors to reduce noise, therefore drain/source strips in layout are also big like 20um or so. Currents flowing in m-side strip add out of phase to the m-side routing line and reduces the inductance of that m-side routing line whereas in p-side routing there is no such phenomenon. This creates inductance mismatch. The easiest fix to this problem is to alter the way current flows through these strips. In existing chip, routing taps the source strips at “outer edges”, if we tap at “inner edges” we would have reduced the mismatch quite much already, and that is what we did in next tapeout. Figure below shows how tapping at inner edges of strips results in +k and -k cancelling each other thus reducing mismatch.

how the way current flows can create mismatch in seemingly symmetric routings

1.8 Measured Results

Table below shows results before and after. LO leakage improved by ~10dBc at lower RF frequencies (below 3GHz) and ~3dB at higher RF frequencies (above 5 GHz). The limited improvement at higher RF frequencies is expected as at such frequencies mixer source node will be sensitive to even couple pH of inductance mismatches which were extremely hard to mitigate as it required complete routing design and floor plan change. This is risky in the sense that improving one thing could ruin other, and most likely team lead or management won’t let you take chances here. If a chip is functional, folks are highly skeptical to touch it unless the failures are critical and specs cannot be relaxed.

\[ \begin{array}{|l|l|l|} \hline \text{Frequency [MHz]} & \text{LOL Before [dBc]} & \text{LOL After [dBc]}\\ \hline 894&-41.1&-51.1\\ \hline 1432&-43.9&-52.4\\ \hline 1962&-39.5&-46.3\\ \hline 2690&-36.7&-44.2\\ \hline 3645&-35.3&-41.6\\ \hline 5000&-34.6&-38.4\\ \hline 5410&-34.0&-37.8\\ \hline 6325&-31.5&-34.9\\ \hline \end{array} \]

1.9 Summary

It was shown that active mixers have strong harmonics of 2\(f_{lo}\) at its source node. Presence of very high harmonics at mixer source node makes it extremely sensitive to routing mismatches. These harmonics mix with odd harmonics of LO and create LO leakage. Our TX suffered from 20pH mismatch in inductance which only shows itself when you take EM model of transistor connection strips into account. Visually symmetric appearing routing lines can easily have small inductance mismatches if magnetic coupling to nearby lines or connections to transistors are not considered.


Published: 26 May 2023
Last Edit: 04 Jun 2023