The post Linearity Improvement Techniques appeared first on RFIC Design.

]]>The Fantastic Four of Linearity Improvement Techniques

Linearity is one of the most, if not THE most, important metric in circuit design. All analog circuits are inherently non-linear mainly because of non-linear behavior of transistors. Many linearity improvement techniques have been discovered or invented in literature yet we only see a few of them in industry practice. This article discusses those few yet fundamental linearity improvement techniques that you must try before you go on with any advance niche solution.

Let’s discuss these techniques in context of V2I converter. A V2I converter or GM cell converts voltage to current, and is usually found in all kind of circuits. For example, it is an essential block in an active mixer based TX as shown in image below. It takes voltage signal from baseband filter (BBF), converts it to current to feed into Gilbert Cell Mixer.

Ok, so say we want to build a linear V2I converter. Let’s start with transistor itself. It’s a natural V2I converter. What’s wrong with it? First off, its g_{m} is a function of signal swing, higher swing leads to higher g_{m}. We want g_{m} to remain fixed over signal swings. Secondly, it does not have any common mode rejection (CMRR). Any variation in DC bias with process or temperature will change the g_{m}. We can resolve this by adding a tail current source. Ok, but how do we fix linearity? We know a resistor is a linear V2I converter, you drop any voltage across it and it produces proportional current (Ohm’s law). It would then be ideal if we could use a resistor for V2I conversion? Yes, but unfortunately there is no direct way we could use a resistor (try to think of a way). First of all, previous stage would need to drive very hard if we put a small resistor, and if we put a big resistor then g_{m} would be pretty low (that would mean its more like a attenuator then amplifier, which is a bummer). Secondly, we need a way of copying current passing through this resistor and feed it to the mixer. It is for latter that we need something more than just a resistor for V2I conversion, and that something more could be a transistor. So that is what folks did. They connected a resistor to a transistor and called it resistive degeneration. The idea is to pass all the voltage at the gate of transistor to the resistor, resistor would convert it to current (which would be very linear), and then transistor can pass that current to the mixer. This works well if the loopgain (g_{m}R) is very very high, otherwise transistor has difficulties passing all the voltage to resistor and drops some voltage across its gate to source (which of course again is function of signal swing, anything with transistor is a function of signal swings really!). But you got some linearity by just using a resistor and transistor, not bad at all. This is where textbook usually stops, and this is where we begin.

There are four basic linearity improvement techniques that are shown in “infographic” below.

Realizing the problem with resistive degeneration was limited loopgain (g_{m}R), one can try to fix it by increasing g_{m} of transistor since we wouldn’t want to change R as it determines our V2I gain. g_{m} can be improved by increasing current of transistor (which is a no no, high current comes with so many issues, not just the power consumption but bigger devices, thicker routing lines, bigger ground bounces, bigger dc offsets, higher noise of bias currents etc.). There are other ways of improving the g_{m}, one of which is called feedback. The idea is to place an opamp before transistor and close the loop on source node of transistor as shown in image below. Opamp would try to force same voltage at its +ive and -ive terminal thereby making the voltage at source node of transistor equal to the input voltage. Voila! this is what we wanted, to pass all the input voltage to resistor. Another way of seeing this is as if transistor g_{m} got boosted by gain of opamp, therefore we also call this linearity improvement technique as g_{m} boosting [4].

Another way of boosting transistor g_{m} is positive feedback. We hear all the time how bad positive feedback it, it make your system oscillate and all that, which is true but its very nature of oscillation (= infinite amplification) can be used to boost g_{m} if employed properly. Caprio’s Quad [3] is one such example as shown in image below. A cross coupled differential pair is introduced between main transistor and degeneration resistor. A cross couple pair has \(\frac{-2}{g_m}\) impedance looking into it which adds to transistor’s g_{m }nulling out the overall g_{m}, and thus variations. Since signal is first fed to main transistor and then feedback happens, this is also called as feedforward linearization.

A more intuitive way of understating it is this: Say M1 received \(V_+\) which increased the current to \(I_+\) while M2 received \(V_-\) which decreased the current to \(I_-\). Now \(I_+\) being higher current would drop higher \(V_{GS}\) across transistor, lets call it \(\Delta V_+\), whereas \(I_-\) would drop smaller \(V_{GS}\), lets call it \(\Delta V_-\). It is the variations of these \(\Delta Vs\) that create signal dependent voltage across resistor. Our goal is to make voltage (\(V_A-V_B\)) across resistor independent of \(\Delta V\) variations which cross couple pair does perfectly by cancelling these variations. Image below shows that \(V_A-V_B\) does not have any \(\Delta V\) when signal traverses the loop (from M1 to M4 to V_{A} to V_{B} to M3 to M2).

The idea of superposition is simple: Add two non-linearities in hope that they cancel each other out. There are different ways this can be accomplished:

Method#1: Say if amplifier A has compressive non-linearity (meaning gain decreases with higher signal) and amplifier B has expansive non-linearity (meaning gain increases with higher signal), A+B would be linear since compression and expansion would compensate each other. Example: take a current source, bias its VDS at its knee point, now any voltage swings at drain of current source would result in expansive current (because swings will take it to triode region where g_{ds} will expand). Add this current to your main amplifier to compensate for its compressive non-linearity.

Method#2: Say amplifier A generates IM3 with some phase \(\phi\), if you could have another amplifier B which generates similar IM3 but with opposite phase \(-\phi\), A+B would be linear. This is not hard to achieve: connect two instances of an amplifier and just bias them at different points, you will already start seeing IM3s subtracting (or adding). Techniques like these are knows as derivative superposition [1].

Method#3: A differential pair g_{m} is very linear right at its bias point but then falls off quickly giving a hump like shape. Good thing is we can move the hump location by setting a different bias point or different device size between +ive and -ive transistor. This means we can take N diff pairs, offset their sizes, add their outputs, and g_{m} would flatten, thus improving linearity. This is shown in image below where two diff pairs are taken. \(V_+\) is given to two transistor with different sizes (one is twice the size of other) and the outputs are added. Total g_{m} can be seen to be flat over wider range of input swings.

If a transistor’s V2I conversion distorts the output by squaring the signal, then same transistor’s I2V distorts the output in an inverse manner (by square-rooting the signal). This means if we cascade I2V and V2I together, the output should be linear. That is precisely what a current mirror accomplishes. You input a current to diode branch, and it gives you perfect replica of it in mirror branch. It takes the current, converts it to voltage (thus *pre*-distorting it by taking square root of it), that distorted voltage is fed to the mirror branch, and replica current comes out (which is clean of distortion because mirror *un*-distorts it by taking square of it). This is awesome, however there is a catch: it is current in and current out. We wanted voltage in and current out. We again need help of our friend resistor. We can add an opamp between drain source terminal of diode branch of current mirror as shown in the image below. The idea is to drop the impedance at node x so much that it acts as a virtual ground, this way all voltage provide by \(V_+\) drops across resistor, and current generated flows through diode transistor which is then mirrored to the output transistor. This circuit is noisy and flicker noise can be high, usually current mirror is degenerated to reduce noise transfer function to output (How? Recall why cascode noise is negligible in a cascode amplifier).

[1] Derivative Superposition – Control of Circuit Distortion by Derivative Superposition Method

[2] PreDistortion – The active-input regulated-cascode current mirror

[3] Caprio’s Quad – Precision Voltage to Current Converter

[4] Regulated Cascode (gm boosting) – A high-swing, high-impedance MOS cascode circuit

aclr (3)
ADS (1)
amplifier (1)
balun (2)
bandwidth (1)
cadence (8)
design (1)
EM (1)
evm (1)
fft (1)
ideal (1)
ideal low pass filter (2)
inductor (2)
intermodulation (4)
IQ calibration (1)
linearity (12)
loadline (1)
LO leakage (1)
matching network (8)
math (6)
mixer (4)
mmwave (1)
noise (3)
product (1)
quality factor (7)
specs (2)
transformer (1)
tx (17)
verilog (1)

RFInsights

Published: 30 Jun 2023

Last Edit: 30 Jun 2023

The post Linearity Improvement Techniques appeared first on RFIC Design.

]]>The post Protected: ACLR Simulation in Cadence appeared first on RFIC Design.

]]>This content is password protected. To view it please enter your password below:

The post Protected: ACLR Simulation in Cadence appeared first on RFIC Design.

]]>The post Ideal Blocks in Cadence appeared first on RFIC Design.

]]>Time to time, debugging or modelling a circuit, we look for ideal blocks in Cadence that can do the job, prove the concept before you go on fully developing the thing. We heard you. Here are some ideal blocks that are already available in Cadence Virtuoso libraries that you can get started from.

Cadence library: ahdlLib/adder

Example use case: Adder can be used for adding signals, for example, if you want to add I and Q signal to generate 45 deg signal.

Cadence library: ahdlLib/subtractor

Example use case: Subtractor can be used when you want to take difference of signals, for example, differential to single ended conversion

Cadence library: ahdlLib/multiplier

Example use case: Multiplier can be used when you want to multiply two signals, for example, you can use it as a mixer. A mixer is an multiplier ideally. You can multiply baseband and LO signal, and at output you should see LO+BB and LO-BB signal.

Cadence library: ahdlLib/amp

Example use case: when you want to scale your signal (amplify or attenuate)

Cadence library: analogLib/delay

Example use case: Adding a delay to signal, for example, you can generate Q signal from I by adding a T/4 delay to it.

Cadence library: analogLib/delayline

Example use case: This blocks also adds a delay and has a characteristic impedance. For example, it can act as an ideal transmission line with some delay.

Cadence library: analogLib/delay

Example use case: We can repurpose delay block to act as a phase shifter. For example, if you want to add phase delay of \(\phi\) at frequency f, you can add \(\dfrac{\phi}{2\pi f}\) delay.

This adds phase delay/lag only, phase advance/lead is not possible with this. To add phase lead, you can add delay to your reference. (afterall you added phase delay wrt some reference, so find that reference, and add delay to it, it will be as if you added phase lead to your intended signal)

Cadence library: rfLib/LNA_PB

Example use case: We can add distortion and noise using this block. For example, if you want excite your power amplifier with some already distorted signal (signal+IM3).

Cadence library: ahdlLib/polynomial

Example use case: This is a very useful block. If you only want to inject particular non-linearity, say only second order harmonics, you can use this block to set the coefficients of polynomial. For example, if you set p3 to zero in image below, it will only create 2nd order non-linearity.

There are many other blocks to be explored in analogLib, ahdlLib and rfLib libraries. For example, you can insert bandpass ideal filters from rfLib/butterworth_bp. We already have a dedicated article on ideal low pass filters. You can use ahdlLib/diffamp as opamp.

This is an extremely useful probe. Sometimes you want to attach something to a node (say for debugging purposes, you want to attach a capacitor to rdegen node shown in image below) that is buried deep in hierarchy, and ripping up that hierarchy or bringing a pin out just for this is way too much work. In this case, you can use analogLib/deepprobe to access that node anywhere in your top level cell.

For example, say we want to access vp node as shown image below. We would insert a deepprobe at top level schematic, and write gm.ich.rdgn.vp (syntax: cell instance name. cell instance name…node name) in its hierarchical node property. This will get us access to the node, and now we can connect whatever we want to this node (like we connected a capacitor in this case).

aclr (3)
ADS (1)
amplifier (1)
balun (2)
bandwidth (1)
cadence (8)
design (1)
EM (1)
evm (1)
fft (1)
ideal (1)
ideal low pass filter (2)
inductor (2)
intermodulation (4)
IQ calibration (1)
linearity (12)
loadline (1)
LO leakage (1)
matching network (8)
math (6)
mixer (4)
mmwave (1)
noise (3)
product (1)
quality factor (7)
specs (2)
transformer (1)
tx (17)
verilog (1)

RFInsights

Published: 16 Jun 2023

Last Edit: 16 Jun 2023

The post Ideal Blocks in Cadence appeared first on RFIC Design.

]]>The post Loadline Design appeared first on RFIC Design.

]]>The output of a power amplifier (PA) is terminated with a specific impedance. This impedance is required for optimal linearity or power generation or efficiency or combination of such specs, and is determined by loadpull analysis. We call it loadline. While a loadline helps PA deliver its performance, the matching (VSWR) gets ruined because we do not present conjugate load to PA. Typically, we insert a circulator between antenna and PA such that reflections don’t reach back to PA, and get absorbed in port 3 of circulator as shown in image below.

This works fine for front-end modules where off-the-shelves blocks can be patched together to curb the ailment. In context of TX RFIC where adding an circulator might not be possible (as they are made of ferrite), we discuss how loadline can be designed while also meeting the VSWR requirements.

Say we have a TX with output resistance R_{o} and output capacitance C_{o}. We have a requirement to present a certain resistance R_{LL} to this TX, and also maintain certain VSWR looking from 50\(\Omega\) port. TX is differential, so we also want to convert it to single ended while doing so. Our job is to figure out how should the white box be designed.

One of the ways we can accomplish this is shown in image below. First, we add a balun to convert differential to single ended. Second, we add a resistor R_{M} to introduce loss into system as we will see later that simultaneous R_{LL} and VSWR requirements cannot be satisfied without adding R_{M} (also see a note on similar topic in appendix). We also add a capacitor C_{T} at primary of balun to tune out primary inductance partially, and C_{L} at secondary to tune out leftover inductance. (We mentioned tuning out primary inductance but not secondary – because there is only one inductance to tune out, the other inductance is a leakage inductance L_{K} which is very small or zero if coupling coefficient is one, see transformer model # 4). One can just use C_{T} or C_{L} to tune out, we distributed the cap because it gives us a knob for loss optimization (more on this later). Our goal is to find R_{L} and C_{L} such that both R_{LL} and VSWR are satisfied. Note R_{L} is not a physical resistor, it the resistance value to which we want our 50\(\Omega\) port to convert to.

Let’s put some numbers in. Say we have 5k\(\Omega\) R_{o} and 100fF C_{o}. We have C_{T}, R_{M}, L_{p}, L_{s}, k, Q_{p}, Q_{s} at our disposal to optimize. We start with 5nH L_{p}. It’s just a guess, you can use any L_{p}, things you would need to consider in choosing L_{p} are:

- how much Q
_{p}are you getting (the higher the better) - what is the self-resonance frequency (the higher the better)
- how much area it takes (the lower the better)
- tuning capability (a higher L
_{p}would need small tuning cap, which makes design very sensitive to parasitic and process variations) - how much k you get (the higher the better)

L_{s} is usually chosen to be 0.707 or 1.414 of L_{p} because this aspect ratio usually gives the highest k. Let’s make R_{M} infinite for now, and choose a random value of C_{T}, and begin! First, let us find what values of resistance and reactance do we need looking into primary of balun, that would get us desired loadline. Let’s call them R_{x} and X_{x}. We believe an analytical solution maybe worked out but we went with iterative solution in Microsoft Excel. We assume some initial value of R_{x} and C_{x}, and start simplifying the circuit till we get to R_{e} and X_{e}. This is shown in image to the right starting from top and ending at bottom. Excel would keep iterating different values of R_{x} and X_{x} until it gets us \(R_e=R_{LL}\) and \(X_e=\infty\), which is what we would want to see pure R_{LL}.

Once we have found R_{x} and X_{x} needed at primary, we can multiply it by turn ratio square and figure out an equivalent RX needed at secondary. We then move this RX step by step towards the output, and finally arrive at R_{L} and C_{L} values. Basically this would mean: attach a C_{L} capacitor at output node, and attach a matching network that transforms port 50\(\Omega\) to R_{L}. If done, your R_{L }C_{L} would transform through balun parasitics and other components we added, and once they make it to TX current source, all the imaginary part would have been stripped off and you should see real R_{LL}.

(Note it is also possible that your matching network transforms port 50\(\Omega\) to R_{L} || X_{L} directly, so one can remove C_{L})

We built an Excel calculator which details these calculations. Different parameters we assumed are in oranges boxes and R_{L} C_{L} values under Final Results. Our goal was 60\(\Omega\) R_{LL}, and our calculator says we need to have \(R_L=50.8\Omega\) and \(C_L=1762.3fF\) to achieve this R_{LL}. Ok great, how about VSWR though? Our Excel sheet does similar calculations for VSWR and shows that we need \(R_L=598.1\Omega\) and \(C_L=453.9fF\) to get 1:1 VSWR. This R_{L} C_{L} is way way off from what we need for R_{LL}. This is not surprising as VSWR is simplify looking for conjugate load which happens to be very different from our desired R_{LL}. In other words, if we had just gone for conjugate match for TX output, our VSWR would have been perfect but we would not have gotten the R_{LL }we wanted.

How can we remedy this situation where we have different R_{L} C_{L} values to meet given R_{LL }and VSWR? By adding R_{M}. See that our loss in image above is 1.66dB, once we add R_{M} we can tradeoff loss with VSWR. Let’s set our VSWR target to 1:1.5. By playing with R_{M }and C_{T }(of course you can play with other variables too, everything is on the table) we can arrive at R_{L} C_{L} values which will give the R_{LL} we want while meeting the VSWR. Image below shows that we don’t need different value of C_{L }now, and R_{L }are still somewhat different but they meet VSWR condition. You can make R_{L }values similar too by reducing R_{M} at the expense of more loss. We are already hitting 3.86dB loss to get 1.5 VSWR. Our finally R_{L} and C_{L }are 49.7\(\Omega\) and 587fF.

Now one might ask that role of R_{M }is clear, but what do we need C_{T }for. Can we get rid of C_{T }and just use C_{L} to tune out balun? The answer is yes but at the expense of slightly higher loss (not always though, devil lies in details, one need to analyze the particular situation). C_{T }was placed strategically. Ideally, we should tune out things where they emerge, meaning we should have tuned L_{p }right where it was (at primary). If we don’t tune it here, and instead try to get the -ive reactive part all the way from C_{L}, it will go through impedance transformations at different nodes (as shown in images above) and at some node if Q is high, it will result in higher loss. How do you know at which node Q is high? You can lookup the Q of all the nodes in our Excel calculator, it’s colored sky blue.

Another question one might ask is if loss gets us VSWR, can we get rid of R_{M }and instead make our balun intentionally lossy (i.e., lower Q)? The answer is not really. It turns out series and shunt losses are different. A series resistor creates two nodes in the circuit and hence creates asymmetry in left and right impedances. For example, if you see that optimum of VSWR and R_{L}_{L} don’t align in frequency that is maybe you got optimum R_{L}_{L} at 2.4GHz but optimum VSWR at 2.5GHz, know that this is because of series resistor somewhere. A shunt resistor keeps this symmetry. Since inductor’s loss is physically a series resistor, we always want to maximize Q to reduce this resistor. Also there are other benefits of putting R_{M} (as shown in our circuit, center of R_{M} goes to supply, we intentionally made it a common mode), this helps in providing even harmonics a path to ground. Otherwise, they will be forced to find a way to circulate in your circuit and create non-linearities you wouldn’t have imagined (like weird combinations of mixing products with your signal, that will land back at your IM3s/5s for example).

Let’s now head to Cadence and plug our numbers in to see if our methodology works. Cadence schematic is shown below. Note that there is no explicit L_{K} here because that was just for our math, real L_{K} is modelled by finite k which we have added in our circuit using “mind” instance in analogLib. Also note that there are two circuits shown but they are exactly the same, just different excitations: one measures R_{L}_{L} and other measures VSWR.

Image below shows simulation results. Our target was 60\(\Omega\) R_{L}_{L }and 1:1.5 VSWR. R_{L}_{L}, VSWR and loss are match pretty well with our calculations.

Excel calculator is attached below. One can start with this calculator to gain insights into circuit (like where is loss coming from, what variable does what, and which variable needs tight control in terms of design sensitivity) and later move on to directly optimize in Cadence.

A subtle difference between mm-wave and RF impedance matching: at mm-wave, transistor output already contains low resistive part (either with existing losses in the circuit or through numerous feedback paths between output and different nodes of circuit that eventually introduce real part in output impedance), therefore one can just go on matching port to transistor output impedance. At RF, real part of output impedance is quite high (almost an open circuit) making it impossible to match to 50\(\Omega\\) because matching network requires very high Q which makes matching very sensitive and low bandwidth. Therefore, we intentionally add a resistor to introduce real part, making things low Q and match-worthy.

(One can think of ways of adding a real part to transistor output impedance without adding resistor itself and that would work too)

aclr (3)
ADS (1)
amplifier (1)
balun (2)
bandwidth (1)
cadence (8)
design (1)
EM (1)
evm (1)
fft (1)
ideal (1)
ideal low pass filter (2)
inductor (2)
intermodulation (4)
IQ calibration (1)
linearity (12)
loadline (1)
LO leakage (1)
matching network (8)
math (6)
mixer (4)
mmwave (1)
noise (3)
product (1)
quality factor (7)
specs (2)
transformer (1)
tx (17)
verilog (1)

RFInsights

Published: 14 Jun 2023

Last Edit: 14 Jun 2023

The post Loadline Design appeared first on RFIC Design.

]]>The post IQ Calibration appeared first on RFIC Design.

]]>Residual sideband suppression (RSB) is one of key TX specs. We want to minimize this because this degrades EVM (when LO is centered to CC leading to signal and its image falling on top of each other) or degrades ACLR (when LO is not centered to CC leading to different signal and image locations). Mismatches in amplitude or phase of I and Q channels in IQ TX generate RSB. Therefore, IQ correction is a usual calibration routine that is followed in industry practice where IQ errors are measured and corrected. We discuss below how it is done in context of TX.

Consider an ideal IQ TX. I channel receives a cosine baseband signal from DAC and multiplies it with cosine LO. Q channel receives a sin baseband signal from DAC and multiplies with sin LO. Multiplication generates two sidebands: \(\omega_{LO}+\omega_{BB}\) aka upper sideband (USB) and \(\omega_{LO}-\omega_{BB}\) aka lower sideband (LSB). When I and Q are summed, one of the sideband cancels. Depending on the sign of “isLSB” (shown in image below), either lower sideband or upper sideband is transmitted, and the one that is cancelled is then called as residual sideband or image. The ratio of residual sideband to transmitted sideband is called as image rejection ratio (IRR). IRR is infinite in an ideal TX with no IQ mismatch.

$$ IRR\;[dBc] = 10\;log \left[\frac{P_{RSB}}{P_{SIG}}\right]$$

where P_{RSB} is RSB power and P_{SIG} is signal power.

Let \(\large \textcolor{#FEDB39}{\epsilon}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \) be the gain and phase mismatch (in radians) between I and Q channels. We can either scale I channel or Q channel to represent gain mismatch. Similarly, we can either add phase shift in I channel or Q channel (LO path or BB path) to represent phase error. The outcome is going to be the same i.e., a given gain and phase mismatch would give a certain RSB no matter where it comes from. Let’s scale the I-channel and add phase shift in Q LO path as shown in image below.

We can write output as follows:

$$ Out = \overbrace{\frac{1+{\large \textcolor{#FEDB39}{\epsilon}}}{2} \biggr[ cos(\Sigma) + cos(\Delta)\biggr]}^{\text{I Channel}} +\overbrace{\frac{isLSB}{2} \biggr[ cos(\Delta+\textcolor{#FEDB39}{\varphi}) - cos(\Sigma+\textcolor{#FEDB39}{\varphi})\biggr]}^{\text{Q Channel}}$$

where \(\Sigma = (\omega_{LO}+\omega_{BB})t\) and \(\Delta = (\omega_{LO}-\omega_{BB})t\)

\begin{alignat*}{4}
\Sigma \text{ Tone}&: \frac{1}{2}& \biggr[ (1+{\large \textcolor{#FEDB39}{\epsilon}}) cos(\Sigma) -isLSB.cos(\Sigma+\textcolor{#FEDB39}{\varphi)} \biggr]\\
\Delta \text{ Tone}&: \frac{1}{2}& \biggr[ (1+{\large \textcolor{#FEDB39}{\epsilon}}) cos(\Delta) +isLSB.cos(\Delta+\textcolor{#FEDB39}{\varphi)} \biggr]
\end{alignat*}

Let’s take squares of these tones since we are interested in ratios of their powers.

$$
\text{Given: } |acos(\Sigma)+bcos(\Sigma+\varphi)|^2 = a^2+b^2+2ab\,cos(\varphi)\;\;\text{(see appendix)}$$
\begin{alignat*}{4}
|\Sigma \text{ Tone}|^2 :& \frac{1}{4}&
\biggr[
(1+{\large \textcolor{#FEDB39}{\epsilon}})^2-isLSB \cdot 2(1+{\large \textcolor{#FEDB39}{\epsilon}})cos(\textcolor{#FEDB39}{\varphi})+1
\biggr]\\
|\Delta \text{ Tone}|^2 :& \frac{1}{4}&
\biggr[
(1+{\large \textcolor{#FEDB39}{\epsilon}})^2+isLSB \cdot 2(1+{\large \textcolor{#FEDB39}{\epsilon}})cos(\textcolor{#FEDB39}{\varphi})+1
\biggr]
\end{alignat*}

If isLSB = -1, that is when we want to keep \(\Sigma\) tone and reject \(\Delta\) tone, IRR will be given as:

$$
IRR = \frac{|\Delta \text{ Tone}|^2}{|\Sigma \text{ Tone}|^2} = \frac{(1+{\large \textcolor{#FEDB39}{\epsilon}})^2- 2(1+{\large \textcolor{#FEDB39}{\epsilon}})cos(\textcolor{#FEDB39}{\varphi})+1}{(1+{\large \textcolor{#FEDB39}{\epsilon}})^2+ 2(1+{\large \textcolor{#FEDB39}{\epsilon}})cos(\textcolor{#FEDB39}{\varphi})+1}
$$

If isLSB = +1, that is when want to keep \(\Delta\) tone and reject \(\Sigma\) tone, IRR will be given as:

$$
IRR = \frac{|\Sigma \text{ Tone}|^2}{|\Delta \text{ Tone}|^2} = \frac{(1+{\large{\textcolor{#FEDB39}{\epsilon}}})^2- 2(1+{\large{\textcolor{#FEDB39}{\epsilon}}})cos(\textcolor{#FEDB39}{\varphi})+1}{(1+{\large{\textcolor{#FEDB39}{\epsilon}}})^2+ 2(1+{\large{\textcolor{#FEDB39}{\epsilon}}})cos(\textcolor{#FEDB39}{\varphi})+1}
$$

That means IRR is same no matter what sideband we transmit which makes sense since IRR should only be dependent upon gain and phase error.

We want to make some measurements to evaulate \({\large \textcolor{#FEDB39}{\epsilon}}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \). These variables are tied together in IRR equation and not separable. We would need numerical techniques to solve this equation, therefore we want to simplify the equation to make IQ calibration easy and intuitive.

Assume \({\large \textcolor{#FEDB39}{\epsilon}} <<1\)\( \; \& \; \textcolor{#FEDB39}{\varphi} <<1 rad\). Let’s look at the denominator of IRR equation:

$$
(1+{\large{\textcolor{#FEDB39}{\epsilon}}})^2+ 2(1+{\large{\textcolor{#FEDB39}{\epsilon}}})cos(\textcolor{#FEDB39}{\varphi})+1\\
$$
$$
=1+{\large{\textcolor{#FEDB39}{\epsilon}}}^2+2{\large{\textcolor{#FEDB39}{\epsilon}}}+2cos(\textcolor{#FEDB39}{\varphi})+2{\large{\textcolor{#FEDB39}{\epsilon}}}cos(\textcolor{#FEDB39}{\varphi})+1
$$
$$\text{Since } \textcolor{#FEDB39}{\varphi}<<1\;\; \implies cos(\textcolor{#FEDB39}{\varphi}) \approx 1-\frac{\textcolor{#FEDB39}{\varphi}^2}{2}$$
$$\therefore 1+{\large{\textcolor{#FEDB39}{\epsilon}}}^2+2{\large{\textcolor{#FEDB39}{\epsilon}}}+2\left[1-\frac{\textcolor{#FEDB39}{\varphi}^2}{2}\right]+2{\large{\textcolor{#FEDB39}{\epsilon}}}\left[1-\frac{\textcolor{#FEDB39}{\varphi}^2}{2}\right]+1$$
$$=1+{\large{\textcolor{#FEDB39}{\epsilon}}}^2+2{\large{\textcolor{#FEDB39}{\epsilon}}}+2-\textcolor{#FEDB39}{\varphi}^2+2{\large{\textcolor{#FEDB39}{\epsilon}}}-{\large{\textcolor{#FEDB39}{\epsilon}}}\textcolor{#FEDB39}{\varphi}^2+1$$
$$=4+4{\large{\textcolor{#FEDB39}{\epsilon}}}+{\large{\textcolor{#FEDB39}{\epsilon}}}^2-\textcolor{#FEDB39}{\varphi}^2(1+{\large{\textcolor{#FEDB39}{\epsilon}}})$$
$$\approx 4 \;\;\because {\large{\textcolor{#FEDB39}{\epsilon}}}<<1$$

Doing similar manipulations on numerator:

$$
(1+{\large{\textcolor{#FEDB39}{\epsilon}}})^2- 2(1+{\large{\textcolor{#FEDB39}{\epsilon}}})cos(\textcolor{#FEDB39}{\varphi})+1\\
$$
$$
=1+{\large{\textcolor{#FEDB39}{\epsilon}}}^2+2{\large{\textcolor{#FEDB39}{\epsilon}}}-2cos(\textcolor{#FEDB39}{\varphi})-2{\large{\textcolor{#FEDB39}{\epsilon}}}cos(\textcolor{#FEDB39}{\varphi})+1
$$
$$\text{Since } \textcolor{#FEDB39}{\varphi}<<1\;\; \implies cos(\textcolor{#FEDB39}{\varphi}) \approx 1-\frac{\textcolor{#FEDB39}{\varphi}^2}{2}$$
$$\therefore 1+{\large{\textcolor{#FEDB39}{\epsilon}}}^2+2{\large{\textcolor{#FEDB39}{\epsilon}}}-2\left[1-\frac{\textcolor{#FEDB39}{\varphi}^2}{2}\right]-2{\large{\textcolor{#FEDB39}{\epsilon}}}\left[1-\frac{\textcolor{#FEDB39}{\varphi}^2}{2}\right]+1$$
$$=1+{\large{\textcolor{#FEDB39}{\epsilon}}}^2+2{\large{\textcolor{#FEDB39}{\epsilon}}}-2+\textcolor{#FEDB39}{\varphi}^2-2{\large{\textcolor{#FEDB39}{\epsilon}}}+{\large{\textcolor{#FEDB39}{\epsilon}}}\textcolor{#FEDB39}{\varphi}^2+1$$
$$={\large{\textcolor{#FEDB39}{\epsilon}}}^2+\textcolor{#FEDB39}{\varphi}^2(1+{\large{\textcolor{#FEDB39}{\epsilon}}})$$
$$\approx {\large{\textcolor{#FEDB39}{\epsilon}}}^2+\textcolor{#FEDB39}{\varphi}^2 \;\;\because {\large{\textcolor{#FEDB39}{\epsilon}}}<<1$$

We can finally write IRR equation as follows:

$$IRR \approx \frac{{\large{\textcolor{#FEDB39}{\epsilon}}}^2+\textcolor{#FEDB39}{\varphi}^2}{4}$$
$$\implies 4 \cdot IRR \approx {\large{\textcolor{#FEDB39}{\epsilon}}}^2+\textcolor{#FEDB39}{\varphi}^2$$

which shows IRR is an equation of circle in plane of \({\large \textcolor{#FEDB39}{\epsilon}}\) and \(\textcolor{#FEDB39}{\varphi}\) with radius of \(2\sqrt{IRR}\). This means there can be different combinations of (\({\large \textcolor{#FEDB39}{\epsilon}}\),\(\textcolor{#FEDB39}{\varphi}\)) that will lead to same IRR.

We can figure out \(\large \textcolor{#FEDB39}{\epsilon}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \) by applying some gain and phase errors ourselves and measuring resultant IRRs as proposed in [3].

- Measure intrinsic \(IRR_1\). Draw the yellow circle with radius of \(2\sqrt{IRR_1}\) and center \((0,0)\). \({\large{\textcolor{#FEDB39}{\epsilon}}}^2+\textcolor{#FEDB39}{\varphi}^2 = 4 \cdot IRR1\)
- Apply a small gain error \({\large\epsilon_a}\) and measure \(IRR_2\). Draw an orange circle with radius of \(2\sqrt{IRR_2}\) and center \(({\large\epsilon_a},0)\) $$({\large{\textcolor{#FEDB39}{\epsilon}}}-{\large{\epsilon_a}})^2+\textcolor{#FEDB39}{\varphi}^2 = 4 \cdot IRR2$$ $${\large{\textcolor{#FEDB39}{\epsilon}}}^2-2{\large{\textcolor{#FEDB39}{\epsilon}}}{\large{\epsilon_a}}+{\large{\epsilon_a}}^2+\textcolor{#FEDB39}{\varphi}^2 = 4 \cdot IRR2$$ $${\large{\epsilon_a}}^2-2{\large{\textcolor{#FEDB39}{\epsilon}}}{\large{\epsilon_a}}+4 \cdot IRR1 = 4 \cdot IRR2$$ $${\large{\textcolor{#FEDB39}{\epsilon}}} = \frac{4(IRR1-IRR2)+{\large{\epsilon_a}}^2}{2{\large{\epsilon_a}}}$$
- Apply gain error \({\large\epsilon_a}\) and small phase error \(\varphi_a\) and measure \(IRR_3\). Draw a green circle with radius of \(2\sqrt{IRR_3}\) and center \(({\large\epsilon_a},\varphi_a)\). $$({\large{\textcolor{#FEDB39}{\epsilon}}}-{\large{\epsilon_a}})^2+(\textcolor{#FEDB39}{\varphi}-\varphi_a)^2 = 4 \cdot IRR3$$ $${\large{\textcolor{#FEDB39}{\epsilon}}}^2-2{\large{\textcolor{#FEDB39}{\epsilon}}}{\large{\epsilon_a}}+{\large{\epsilon_a}}^2+\textcolor{#FEDB39}{\varphi}^2-2\textcolor{#FEDB39}{\varphi}\varphi_a+\varphi_a^2 = 4 \cdot IRR3$$ $$4 \cdot IRR2 -2\textcolor{#FEDB39}{\varphi}\varphi_a+\varphi_a^2 = 4 \cdot IRR3$$ $$\textcolor{#FEDB39}{\varphi} = \frac{4(IRR2-IRR3)+\varphi_a^2}{2\varphi_a}$$

Thus, you can calculate gain and phase errors by making three measurements. Graphically, it is the point where the three circles overlap.

(Tip: . A quick sanity check of phase error sign is to see if the IRR3 was better than IRR2. In that case, phase error that you applied partially cancelled the phase error in the system, therefore we can say the phase error in the system is of opposite polarity than what we applied. If IRR3 is worse than IRR2, then phase error in system has same polarity as of phase error you applied.)

Once you have figured out \(\large \textcolor{#FEDB39}{\epsilon}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \), you can correct the system by scaling say I channel by \(\frac{1}{1+{\large \textcolor{#FEDB39}{\epsilon}}}\) and adding phase of \(-\textcolor{#FEDB39}{\varphi} \). However, adding a phase shifter block in digital front end (before DAC in digital domain which is most likely or more plausible place to add calibration circuitry) is not very hardware friendly. We want to work with adders or multipliers. Therefore, we need to work on equivalent representation of \(\large \textcolor{#FEDB39}{\epsilon}\)\( \; \& \; \textcolor{#FEDB39}{\varphi} \) as suggested in [1,2].

Consider Q channel baseband and LO multiplication, we can write it as follows:

$$isLSB.sin(\omega_{BB}\,t) \times sin(\omega_{LO}\, t+\textcolor{#FEDB39}{\varphi})$$
$$isLSB.sin(\omega_{BB}\,t) \times [sin(\omega_{LO}\,t)cos(\textcolor{#FEDB39}{\varphi})+cos(\omega_{LO}\,t)sin(\textcolor{#FEDB39}{\varphi})]\;\; \because sin(a+b)=sin(a)cos(b)+cos(a)sin(b)$$

that is instead of saying phase error we can say it was a multiplication error as if our Q-channel LO was sin LO multiplied with \(cos(\textcolor{#FEDB39}{\varphi})\) and cos LO multiplied with \(sin(\textcolor{#FEDB39}{\varphi})\). We can make our LO error free and model phase error shown below.

so our IQ TX with gain and phase errors is equivalent to figure in bottom left that is we can model gain and phase errors by gain scaling \(\textcolor{#57ACDC}{\alpha}\) and IQ cross talk \(\textcolor{#57ACDC}{\beta}\).

$$\textcolor{#57ACDC}{\alpha} = \frac{1+{\large \textcolor{#FEDB39}{\epsilon}}}{cos(\textcolor{#FEDB39}{\varphi})}\;\;\;\text{&}\;\;\; \textcolor{#57ACDC}{\beta} = tan(\textcolor{#FEDB39}{\varphi}) $$

We can calibrate the errors by doing opposite as shown in image below. This circuitry will be added in digital front end where data of I channel will be scaled by \(\frac{1}{\alpha}\) and \(-\frac{\beta}{\alpha}\) of Q data will be added to it. Once this data is send on I channel, it will correct the gain and phase errors of system. We can send the Q data as it is to Q channel, we don’t need to add/multiply anything to it.

We built an IQ TX in Cadence using ideal blocks like multipliers, summers and delay elements from ahdlLib library as shown in image below.

We added gain error of 0.075 to I channel BB and phase delay of 1.25 degree to Q channel LO. Our goal is now get these numbers from calibration algorithm presented above. We measure (or simulate in this case) raw IRR1, IRR2 with gain error of 0.01 applied and IRR3 with gain error of 0.01 and phase delay of 1 degree applied. Three measured numbers are shown in image below.

We made an Excel calculator (which is available to download below), plugged these numbers in, and this give us our calculated gain and phase error to be 0.071 and -1.26 degree (means delay). Hmm this is close but does not quite match the actual gain and phase errors in system which were 0.075 and -1.25 degree to be precise.

Let’s see what happens when we compute our \(\alpha\) and \(\beta\), and use them for correction of IRR. Image below show IRR before and after calibration.

IRR improves from -28dBc to -54dBc after IQ calibration. Good but not perfect. So what is missing? Remember we assumed \({\large \textcolor{#FEDB39}{\epsilon}} <<1\)\( \; \& \; \textcolor{#FEDB39}{\varphi} <<1\), this got us. Our calculator could not calculate exact gain and phase error because of this assumption. If you desire to calibrate IRR much better than -50dBc levels, then you would need to get back to original equation of IRR, and use that to calculate errors (instead of circle equation). This is also the reason we applied very small gain and phase errors (0.01 and 1 degree) so that overall gain and phase error (what we applied + what’s already in system) does not exceed our assumption of \({\large \textcolor{#FEDB39}{\epsilon}} <<1\)\( \; \& \; \textcolor{#FEDB39}{\varphi} <<1\). This is also an issue. Your system might not be able to apply such small gain and phase errors. In that case too, you need use original IRR equation. Calibration algorithm remains same. Excel can solve such equation by numerical techniques (like hit and trial).

Image below plots IRR with circle equation (dotted lines) and actual equation (solid lines). We can already see for gain error of 0.1 or more, the circle equation and actual equation don’t match. However, if gain and phase errors are small (i.e., for intrinsic IRRs better than -30dBc), circle equation is good enough.

[1] Wideband Digital Correction of I and Q Mismatch in Quadrature Radio Receivers (Hardware Friendly Implementation)

https://ieeexplore.ieee.org/document/857556

[2] I/Q Imbalance Calibration in Wideband Direct Conversion Receivers

https://ieeexplore.ieee.org/document/7790607

[3] A Low-Complexity I/Q Imbalance Calibration Method for Quadrature Modulator (Calibration Algorithm)

Summation of two vectors with phase \(\textcolor{#FEDB39}{\varphi}\) between them.

Assume a vector \(acos(\Sigma)\) and a scaled phase shifted version of it \(bcos(\Sigma+\textcolor{#FEDB39}{\varphi})\). We show in image below how can we calculate magnitude of their sum (vector Z).

RFInsights

Published: 04 June 2023

Last Edit: 04 June 2023

The post IQ Calibration appeared first on RFIC Design.

]]>The post Protected: LO Leakage in TX appeared first on RFIC Design.

]]>This content is password protected. To view it please enter your password below:

The post Protected: LO Leakage in TX appeared first on RFIC Design.

]]>The post Impedance Matching and Quality Factor appeared first on RFIC Design.

]]>Chp. 7: Quality Factor and Impedance Matching

One Must Not Tell Lies.

We have reached the finale of this saga. We have discussed how quality factor of a resonator led to signal gain and how did RF designers used that gain to boost impedance. Today we will look at how can we finally make a matching network out of this, and also a debunk a lie that has been and is continued being sold: “Bandwidth of matching network equals inverse of quality factor.”

Say you want to match 50Ω to 1000Ω at 1GHz. Let’s take two 50Ω resistors and insert a 1GHz LC resonator between them. We know that voltage across reactance is Q times larger than resistance in a series resonator. We are going to exploit this and move a resistor across a reactance to tap this voltage gain. The moment you do that, the voltage gain drops heavily because that reactance just cannot drive this small resistor (after all its not an active amplifier). What we need to do now is to boost the resistor value by 1+Q^{2} to keep tapping that voltage gain. Now you have the opportunity to choose Q. Choose it in a way that the resistor becomes 1000Ω, and that Q comes out to be 4.36 as explained in image below. So you know now that you want your LC to resonate at 1GHz with Q of 4.36. From this information, you can figure out L and C values. So, that’s that. You have a series RLC resonator which will match the impedance if you place the resistor across reactance. And once you place it, of course you raise the resistor value from 50Ω to 1000Ω to keep Q intact. Which reactance do you place it across? Capacitive or Inductive? You can choose any. If you place it across capacitor, it will be a lowpass matching network. If you place it across inductor, it will be a highpass matching network. The latter is mostly preferred choice since you can use capacitor to DC block output and inductor to provide voltage bias to chip. And this is how L-matching networks were discovered by exploiting properties of a resonator.

One of the common misconception that is found among RFIC designers (or should we dare to say a lie that is sold to them) is that bandwidth of a matching network is equal to inverse of Q. Right? You have seen this:

$$ Q = \frac{1}{FBW}$$

where FBW is fractional bandwidth \(\dfrac{\Delta \omega}{\omega_o}\) and \(\Delta \omega\) represents 3dB bandwidth around your center frequency \(\omega_o\).

But we are no longer going to be fooled by this. We discovered in previous chapter that this is actually bandwidth of a resonator, and although matching network is derived from resonator, at the end of the day it is not a resonator. Think about how can it resonate, it has an L shape! Only series or parallel LC resonate. Period. Therefore, \(\frac{1}{Q}\) does not equal to 3dB bandwidth of matching network. Image below shows 3dB bandwidth for three cases discussed above: Series RLC resonator, low pass L-match, and high pass L-match. We can see they all have different 3dB BW. For resonator it is equal to \(\frac{2}{Q} = 0.458\;FBW \approx458MHz \), but no so much for others.

(Its **\(\frac{2}{Q}\) not \(\frac{1}{Q}\)** because quality factor of series RLC resonator is halved – think about it, there are two 50Ω resistors – we worked out Q of 4.36 with respect to 50Ω but total series resistance is 100Ω, hence Q is halved. This is good for you because you get twice the BW)

So even though Q does not predict exact bandwidth for matching network, it does serve as a pretty good indicator of bandwidth. You can for sure infer that if Q is high, bandwidth is going to be low. So the question then is what is the bandwidth of matching network, and does it ever equal to resonator bandwidth? Unfortunately, the exact bandwidth of matching network needs to be calculated by circuit analysis. We have not found a “magic formula” for it. The good news though is that bandwidth is almost to resonator bandwidth when Q is high. This makes sense because the series-parallel transformation that we did holds across frequencies when Q is high to begin with. For example if Q is 20, then even if it varies across frequency, say from 19 to 21 across frequency, that is relatively a small change. But if you began with a small Q, say Q of 3, and now if it varies across frequencies from say 2 to 4, that is a huge change. Your series-parallel transformation with these Qs will result in very different values of boosted R (we mean R(1+Q^{2})). And since you have a fixed R attached across reactance (1000Ω in our case), your impedance transformation will be ruined, and behavior of L-match will start differing from behavior of resonator across frequency – hence different bandwidths.

Next question: how different is L-match bandwidth from resonator bandwidth. Let’s say you would settle for 5% inaccuracy in bandwidth, that is if \(\frac{1}{Q}\) gives a bandwidth which is within 5% of actual bandwidth, you would say “meh, ok, I take it, I don’t want to calculate exact bandwidth anyway, it does not matter much for me, all I care about is that I could easily design matching network with Q-factors and I have a rough idea that \(\frac{1}{Q}\) bandwidth is going to be close enough to my actual bandwidth”. In that case, we recommend to ensure Q of your L-match is greater than 5 for low pass L-match, and greater than 8 for high pass L-match, then you are guaranteed to have less than 5% bandwidth difference as shown in image below.

Image above also shows how quickly bandwidth delta grows for lower Q. For example, if Q of your L-match is less than 3, you can clearly see bandwidth delta is greater than 100% (for highpass L-match), that is your actual bandwidth is going to be much higher than what is predicted by Q of your circuit.

Alright folks – this concludes our journey from resonance to impedance matching. Hope you had fun taking this journey and it was insightful.

RFInsights

Published: 11 March 2023

Last Edit: 11 March 2023

The post Impedance Matching and Quality Factor appeared first on RFIC Design.

]]>The post Quality Factor and Bandwidth appeared first on RFIC Design.

]]>Chp. 6: Quality Factor and Bandwidth

Q-factor is Inverse of 3dB BW. Design or Coincidence?

You have seen this

$$ Q = \frac{1}{FBW}$$

Now let’s change C up and down keeping L fixed, resonance frequency changes again down and up respectively, and Q changes too (this time by \(\frac{1}{f}\) fashion though because reactance of capacitor changes by \(\frac{1}{f}\) fashion)

The point of this exercise is to realize that Q and frequency indeed have a relation. Let’s put the two curves on top of each other as shown in right image. We observe for a \(\Delta \omega\), there is a \(\Delta Q\) indicating that there is a relation between bandwidth and quality factor – that’s our cue. Let’s focus on yellow curve for now and write this down in math:

(yellow because math is easier, \(\frac{E_S}{P_D}\) remains same over frequency as we mentioned before, the math of red curve is in appendix and leads to same conclusion what we are going to draw below).

$$Q_o = \omega_o \frac{E_S}{P_D};\;\;\;Q_H = \omega_H \frac{E_S}{P_D};\;\;\;Q_L = \omega_L \frac{E_S}{P_D}$$
$$ Q_H - Q_L = (\omega_H - \omega_L) \frac{E_S}{P_D}$$
$$\Delta Q = \Delta \omega \frac{E_S}{P_D}$$
$$\Delta Q \times \omega_o= \Delta \omega \frac{E_S}{P_D} \times \omega_o$$
$$\Delta Q \times \omega_o= \Delta \omega \times Q_o$$
$${\LARGE \textcolor{#40CE7F}{\frac{\Delta Q}{Q_o} = \frac{\Delta \omega}{\omega_o}}}\;\;\; (1)$$

This gives us interesting insight that your bandwidth relative to your center frequency is equal to change in Q relative to Q at center frequency. If you allow \(\Delta Q\) to be bigger, you can get wider bandwidth. Or if you *decrease* Q_{o}, you get wider bandwidth too. This answers our first question that how bandwidth and quality factor turned out to be inversely related, and that this relation was hidden inside the classical Q-factor formula itself.

Now to the 2^{nd} question: how come \(\Delta \omega\) turned out to be 3dB BW and not some x dB? Was it by design or a pure coincidence that our beloved half power bandwidth concept naturally landed as being equal to inverse of Q (and we mean not just proportional to inverse of Q but exactly equal to inverse of Q). To understand this, think of parallel RLC tank. When does power drop by 3dB? When current through resistor goes down to 0.707I where I was the current at resonance. For current to drop to this level, X of the tank needs to be equal to R (don’t be fooled by reactance – you might think X=R will lead to half half current division, that is not correct, because X never draws current in phase with R, so there is always a chance that R could get more from source even though X=R, if it were two Rs, then yes they draw same amount of current from source at same time (means in phase) so source current has to get divided half and half). Ok, so for 3dB power, we can write that tank susceptance needs to be equal to tank conductance:

$$|B_L - B_C| = G $$
$$\left|\frac{B_L}{G} - \frac{B_C}{G}\right| = 1$$
$$\left|\frac{R}{X_L} - \frac{R}{X_C} \right| = 1$$
$$|Q_L - Q_C| = 1 $$
$$\Delta Q = 1 $$

This says the frequencies where the difference between tank reactances gets equal to tank resistance or in other words, where \(\Delta Q\) gets equal to 1, are 3dB frequencies. Insert this in Eq. (1)

$$\frac{1}{Q_o} = \frac{\Delta \omega}{\omega_o}$$
$${\LARGE \textcolor{#40CE7F}{Q_o = \frac{\omega_o}{\Delta \omega} = \frac{1}{FBW}}}$$

This answers our second question that \(\Delta \omega\) is not just any bandwidth but actually 3dB BW when \(\Delta Q\) is one, and with that the inverse of Q is exactly equal to fractional BW.

This has to do with capacitor. We said 3dB BW occurs when tank X becomes equal R. Tank X is basically delta between ind X and cap X. Notice how quickly this delta grows on the left side of resonance because of \(\frac{1}{f}\) behavior of capacitor’s reactance. On the other hand, delta grows slowly on right side because capacitor’s reactance decay slows down (again \(\frac{1}{f}\) behavior). This gives right side advantage, and it takes more frequencies for delta to grow equal to R on right side, thus giving more BW at right side. Think of series RLC circuit. Image below plots ind reactance X_{L}, cap reactance X_{C}, their delta X_{L}-X_{C}, and how fast this delta grows \(\frac{d}{df} (X_L-X_C)\). Y-axis is R of the RLC, and x-axis is frequency. You can see if Q of the tank is big (i.e., R is small e.g., R=1), the reactance delta (orange color) takes almost same frequencies left and right to become equal to R. If Q is small (look at R=10), you can see reactance delta becomes quickly equal to R=10 on left side (thus lesser BW on left) but takes more frequencies at right side (thus higher BW on right).

It is interesting to note that if capacitor behaved linearly with frequency, that is if \(X_C= -2 \pi fC\), then left and right side BW would have been equal. A negative inductor can do that. So if you knew why this left and right side BWs were different, and if they mattered that much in your system, you would quickly have thought of how can design you design a negative inductor, because that will solve your problem. If you didn’t know, you wouldn’t think of negative inductor as well. That is why we dive deep into these articles. Innovation lies in strong fundamentals, not complex circuits.

$$R=1 \implies (0.9235,1) \;\;\;\text{&}\;\;\; (1.0827,1)$$
$$R=5 \implies (0.6783,1) \;\;\;\text{&}\;\;\; (1.474,1)$$
$$R=10 \implies (0.4822,1) \;\;\;\text{&}\;\;\; (2.0737,1)$$

What can you say about central tendency of this data set? If you take arithmetic mean of these points, it would come out different for each pair but you take geometric mean, it would come out equal to 1 which is correct as you can see visually in above image too. This means the central point of this data is geometric mean.

$$R=1 \implies (0.9235,1) \;\;\;\text{&}\;\;\; (1.0827,1) \implies AM =1.003 \;\;\; \text{&} \;\;\; GM=1$$
$$R=5 \implies (0.6783,1) \;\;\;\text{&}\;\;\; (1.474,1) \implies AM =1.076 \;\;\; \text{&} \;\;\; GM=1$$
$$R=10 \implies (0.4822,1) \;\;\;\text{&}\;\;\; (2.0737,1) \implies AM =1.278 \;\;\; \text{&} \;\;\; GM=1$$

But then again, why did this happen? Answer: because of capacitor’s reactance \(\frac{1}{f}\) behavior with frequency. The reactance delta of tank is given as:

$$X_L - X_C$$
$$\omega L - \frac{1}{\omega C}$$

Let’s see how fast this delta changes with frequency. Take derivative of it:

$$\frac{d}{d\omega} \left(\omega L - \frac{1}{\omega C}\right) \implies \left[L + \frac{1}{C}\frac{1}{\omega^2}\right]$$

This shows that reactance delta grows by \(\frac{1}{f^2}\), that is at every next frequency the new value of reactance delta is given by *this much times of previous value* rather than *this much addition on previous value*. And that is a characteristic of geometric series, hence the center frequency ends up being geometric mean, and that is also why if you look at resonator response at x times higher or x times lower frequency than resonance, you would see it develops same amplitude. But you if you were to look at resonator response at +x frequency and -x frequency from resonance frequency, you would find different amplitude.

For record, let’s just derive it in a pure mathematical too. Recall from above:

$$Q_o = \omega_o \frac{E_S}{P_D};\;\;\;Q_H = \omega_H \frac{E_S}{P_D};\;\;\;Q_L = \omega_L \frac{E_S}{P_D}$$
$$ Q_HQ_L = \omega_H \omega_L \frac{E_S^2}{P_D^2}$$
$$ \omega_o^2 \times Q_HQ_L = \omega_o^2 \times \omega_H \omega_L \frac{E_S^2}{P_D^2}$$
$$ \omega_o^2 \times Q_HQ_L = \omega_H \omega_L \times Q_o^2 $$
$$ \omega_o^2 \times \frac{R}{X_H}\frac{R}{X_L} = \omega_H \omega_L \times \frac{R^2}{X_o^2} $$
$$ \omega_o^2 \times \frac{1}{\omega_H L}\frac{1}{\omega_L L} = \omega_H \omega_L \times \frac{1}{\omega_o^2 L^2} $$
$$\implies \omega_o^2 = \omega_H \omega_L$$
$$\implies {\LARGE \textcolor{#40CE7F}{\omega_o = \sqrt{\omega_H \omega_L}}}$$

Having developed the insights behind Quality factor and Bandwidth, the situation is now ripe to proceed to matching networks – a topic for next chapter.

Derivation of Quality factor and Bandwidth relation from Capacitor’s reactance (red curve)

$$Q_o = \omega_o \frac{E_S}{P_D};\;\;\;Q_H = \omega_H \frac{E_S}{P_D};\;\;\;Q_L = \omega_L \frac{E_S}{P_D}$$
$$ Q_H - Q_L = \frac{1}{P_D} \left[ \omega_H E_H - \omega_L E_L \right] $$
$$ Q_H - Q_L = \frac{1}{P_D} \left[\omega_o E_S \frac{\omega_o}{\omega_H} - \omega_o E_S \frac{\omega_o}{\omega_L} \right] \;\;\; \text{(because if you increase f by x, tank's Q and thus } \omega_o E_s \text{ drops by } \frac{f_o}{x} \text{ )}$$
$$ \Delta Q = \omega_o \frac{E_S}{P_D}\omega_o \left[\frac{1}{\omega_H}-\frac{1}{\omega_L}\right]$$
$$ \Delta Q = Q_o \omega_o \left[\frac{\omega_L-\omega_H}{\omega_H \omega_L}\right]$$
$$ \frac{\Delta Q}{Q_o} = \omega_o \left[\frac{\Delta \omega}{\omega_o^2}\right]$$
$$ \frac{\Delta Q}{Q_o} = \frac{\Delta \omega}{\omega_o}$$

RFInsights

Published: 09 March 2023

Last Edit: 09 March 2023

The post Quality Factor and Bandwidth appeared first on RFIC Design.

]]>The post Transient response of LC Tank appeared first on RFIC Design.

]]>Chp. 5: Quality Factor and LC Tank Behavior in Time Domain

To develop further intuition in Q-factor and extend its application to matching and bandwidth, it is prudent to study time domain behavior of LC tank. We show how an LC tank starts up, how the voltage developed across it heads to infinity, how a finite Q-factor limits its growth, and what happens if you excite the tank with non-resonant frequencies.

Attach a sinusoidal current source of 1mA with 1GHz frequency to an LC tank which is also set to resonate at 1GHz. Let’s see how things play out.

**V1:**Current through inductor cannot change instantly. It begins slow letting cap take all the source current.

**V2:**There is only limited current available from source. As inductor starts taking more and more current, cap current decreases.

**V3:**Inductor has taken all the current. Cap current goes to zero and cap reaches max voltage because it did not discharge so far. It had been charging and charging. Now we can appreciate why we say current leads the voltage in capacitor by 90 deg.

**V4:**Inductor had taken all the source current but now source current is falling, that is a sudden change for inductor which cannot happen. It needs to keep going, so cap kicks in. It discharges by providing inductor extra current it needed. Watch the inductor current – it has risen above source level. Can we call it current gain? Yes if we can control it, and we will.

**V5:**Cap charge exhausted. Cap voltage is zero, and source current is zero too. See how did source and cap zero crossing aligned. This will prove to be important later on.

**V6:**Source reverses the direction, and starts charging the cap in opposite direction. Inductor still has positive current going and it just cannot change its direction like that. So, it flips the voltage around it to maintain the current direction and starts providing charge to cap. Watch the current – it has risen to a higher level than before.

**V7:**Inductor has exhausted all the energy it stored. Cap keeps taking current from source.

**V8:**Inductor also begins to take the current in reverse direction now. Cap and ind both share source current.

**V9:**Soon ind again takes all the current from source leaving nothing for cap. No more charge current available to cap? so then it has reached its max voltage (in negative direction now)

**V10:**Source current is again reducing but ind has to keep going because again ind does not allow sudden current change. So cap kicks in again and start providing for ind. You see the cycle here? How the other guy kicks in when source is not able to provide. This keeps going and in each cycle current rises to a new level than before. They keep exchanging charge between themselves plus keep taking more charge from source. Result? This is heading to infinity.

**V11:**Source reaches zero crossing and so does cap voltage. Cap has got no charge now, its all the ind current which is flowing between them, therefore the direction is opposite i.e., ind sourcing and cap sinking. Now we can appreciate why we say ind and cap current is always out of phase in parallel LC tank.

**V12:**Source wants to charge cap in positive polarity now. Ind says no. I cannot take positive current at the moment. Let me first get rid of my build-up current (or magnetic field whatever you want to call it). Voltage is flipped again and ind starts charging the cap.

We are going to do same experiment as above but now with an LC tank with finite quality factor. Let’s attach a resistor of 1kΩ to an LC tank set to resonate at 1GHz, and excite this tank with 1mA current source with 1GHz frequency.

**V1:**Current through inductor cannot change instantly. It begins slow letting cap take all the source current. Voltage developed across tank is also very small at this point, so resistor also does not draw in much current.

**V2:**Ind current keeps taking more current from source and so does resistor.

**V3:**Time comes when ind and res has taken all the current from the source. Cap current falls to zero, and cap has reached max voltage. But note that this time the voltage is lesser compared to the case with no resistor (229mV vs 285mV). This is an early indication that source just does not deliver all its charge to tank now, some part of it gets lost in resistor.

**V4:**Ind needs to keep going but source is decreasing. Resistor can follow source but for inductor that is a sudden change. Cap kicks in and starts delivering its charge to inductor.

**V5:**Source exhausted and so did cap voltage. Inductor current reaches its maxima because there is no one left now to provide any charge. See how resistor was able to follow tank voltage but inductor has its current at peak instead when voltage collapsed. Now we can appreciate why we current in inductor lags the voltage by 90 deg.

**V6:**Source wants to charge cap in opposite direction now. Ind cannot flip the current suddenly, so it flips the voltage, and starts discharging through cap. Resistor is kind. It follows whatever LC are trying to do. Whatever voltage they develop, resistor only draws that much current.

**V7:**Ind current has collapsed. Cap keeps taking current from source but watch now res is drawing more and more current from source as time progresses, leaving less and less for cap to build-up its charge.

**V8:**Inductor also begins to take the current in reverse direction now. Cap, ind and res – all share source current.

**V9:**Time comes when ind and res has taken all the current from the source. Cap current falls to zero, and cap has reached max voltage (in opposite polarity). But note that this time the voltage is lesser compared to the case with no resistor (519mV vs 753mV). An indication that voltage build-up is slowed down, and maybe will stop at some point? We will see.

**V10:**Source is falling but ind has to keep going. Cap kicks in, discharging through ind and giving it the extra current it needed. You can also observe that current has not risen to the levels it had risen when there was no resistor. You can also think of it this way: there is no resistor but current source has just reduced from 1mA to x mA, and this x is reducing with time. And after things are past transient period, this x will eventually go down to zero.

**V11:**Source reaches zero crossing and so does cap voltage. Look at res current waveform now – see how it is almost becoming equal to source current – leaving very little for ind and cap.

**V12:**Source wants to charge cap in positive polarity now. Ind says no. I cannot take positive current at the moment. Let me first get rid of my build-up current. Voltage is flipped again and ind starts charging the cap. Source also wants to charge cap but now resistor is starting to take almost all of its current (resistor’s demand is going up and up because voltage across tank has been growing up and up)

- Left image: L=50n, C~0.5p to resonate at 1GHz, no R, thus Q=inf. Each cycle ind and cap exchange charge between them plus current source adds in too. Total charge/current/voltage/energy whatever you like, keeps on adding up. This is headed to infinity.

- Middle image: Same LC but with R=1kΩ, thus Q=3.2. Each cycle ind and cap exchange charge between them plus current source adds in too. But with time resistor draws more and more current from source until it has taken all the current and leaves nothing for LC tank. Charge in tank stops piling up. Whatever LC could store, that is going to be the voltage or current in the tank. We can clearly see current in LC tank is Q times higher than source or resistor current. You can call it amplification at this time (instead of oscillation), and make use of this current gain, just like we used voltage gain for impedance transformation.

- Right image: Same LC tank but with R=2kΩ now, which doubles the Q to 6.4. Now observe. Resistor is doubled, meaning for it to absorb all the current, voltage has to reach 2V, that means LC tank has more time or cycles in taking the charge from source current. That is why the current in tank could now build up to 6mA! So in essence, a higher quality factor is just giving tank more time to take in more from source, and thus results in bigger current gain. This aligns with our expectation that quality factor is nothing but number of cycles it takes for a resonator to lose (or build) the energy.

- One more thing to observe: when there was no resistor, current in LC tank was rising in a linear fashion. However, with a resistor, it rises exponentially. This has to do with fact that RC charging and discharging is exponential in nature.

If you force an LC tank at a frequency which is not natural to it (and that is everything except resonant frequency), it wouldn’t be able to develop the max voltage it could or in other words current source would never be able to deliver the power it could in resonant case. Ind and cap will always take in some current from source, leaving a little less for resistor. Therefore, voltage developed will always be smaller than a resonant case. We compare two cases. Our LC tank was set to resonate at 1GHz, we excite it with double (2GHz) and half (0.5GHz) frequency and analyze why it could not develop much voltage.

Things play out as usual. Cap and resistor start by taking all the current from source. Ind picks up the pace, and slowly starts taking current. A point comes where not enough current is available from source to keep providing for all three (ind, cap, res). Someone has to give up. Ind cannot because it does not like sudden change in current. Cap gives up and its current starts reducing. All of this looks normal transient behavior as we saw in case of resonant frequency. The difference comes from zero crossings. See now cap voltage and source currents zero crossings are not aligned which they were in resonant case. So at V1 (in left image below) cap is in a position to discharge but source still wants to go positive. Its zero crossing comes later at V2. Now instead of reverse charging the cap and ind also helping the process (as happened at V6 for resonant frequency cases described above), source tries to charge cap positively again whereas ind is still trying to reverse charge. Overall, result is that total charge or voltage build-up across cap is lesser. This goes on in every cycle, and cap is never able to develop a higher voltage. Now question is how much lesser voltage is produced compared to resonant case? Ans: the farther the zero crossing of cap voltage from source current, the lesser the voltage developed. It does not matter if source zero crossing comes earlier or later, what matters is how far away is it.

Note left and right image below are response of same LC tank. Just that left shows initial transient behavior, and right shows when things have settled.

Nothing much to say here. It emphasizes the same thing that when zero crossings are not aligned, things will not go in your favor. For example, you can observe that resistor current and source current are not in phase, so the resistor would never be able to draw all of source current and develop the max voltage it could. And they are not in phase because the way cap voltage developed and when source zero crossing came in didn’t align (V1 and V2 in left image below).

The LC tank of 1GHz resonance frequency and quality factor of ~3 is excited with different frequencies and the voltage developed across tank is plotted in image below.

Interesting thing to note here that is that if you excite at x times higher or x times lower frequency than resonance frequency, the voltage developed is same. For example, at \(1.1f_o\) or \(\dfrac{f_o}{1.1}\), the voltage developed is about 854mV. Similarly, at \(1.33f_o\) or \(\dfrac{f_o}{1.33}\) voltage developed is again same (~477mV). This tells us that a resonator behaves in a geometric fashion that is if you were to look at voltage developed at \(f_o+x\) and \(f_o-x\) it will not be same; but if you were to look at \(xf_o\) and \(\dfrac{f_o}{x}\), it will be exactly the same. How can we explain this – let’s explore that in next chapter.

RFInsights

Published: 04 March 2023

Last Edit: 04 March 2023

The post Transient response of LC Tank appeared first on RFIC Design.

]]>The post Series to Parallel Conversion – Intuition appeared first on RFIC Design.

]]>Chp. 4: Series to Parallel Conversion using Quality Factor

The Underrated Magic Trick

A series impedance can be transformed to equivalent parallel impedance and vice versa. This is the most underrated trick yet it is fundamental to matching network design. Math behind series to parallel conversion is simple. You want to know when a series impedance is equal to parallel impedance, so you equate them.

$$ R_s + jX_s = R_p \,||\, jX_p $$
$$ R_s + jX_s = \frac{jR_pX_p}{R_p+jX_p}$$
$$ R_s + jX_s = \frac{R_pX_p^2}{R_p^2+X_p^2}+j\frac{R_p^2X_p}{R_p^2+X_p^2}$$
$$ R_s + jX_s = \frac{R_p}{\frac{R_p^2}{X_p^2}+1}
+j\frac{X_p}{1+\frac{X_p^2}{R_p^2}}$$
$$ R_s + jX_s = \frac{R_p}{Q^2+1}+j\frac{X_p}{1+\frac{1}{Q^2}}$$
$${\large \textcolor{#40CE7F}{\implies R_p = R_s\,(1+Q^2) \;\;\;\text{&}\;\;\; X_p = X_s \left(1+\frac{1}{Q^2}\right)}} $$

This says a series R_{s} is boosted by factor (1+Q^{2}) when it is converted to a parallel resistance, and a series reactance X_{s} is boosted by factor (\(1+\frac{1}{Q^2}\)) when it is converted to a parallel reactance. For Q>>1 (or practically Q>4) this translates to

$${\large \textcolor{#40CE7F}{\implies R_p = Q^2R_s\;\;\;\text{&}\;\;\; X_p = X_s \;\;\; (1)}} $$

This means a resistor got boosted but reactance stayed same which is strange. Let’s explore the physical explanation of why is it so.

Excite a series RL circuit with voltage V_{S} as shown in image below.

$$ V_S = V_R + j QV_R $$
$$ V_S = V_R(1+jQ)$$
$$|V_S| = |V_R|\sqrt{1+Q^2} \;\;\;\; (2) $$
$$\implies |V_R| = \frac{|V_S|}{\sqrt{1+Q^2}} $$

Power dissipated by resistor can be given as:

$$ P = \frac{1}{2}\,\frac{V_R^2}{R} $$
$$ P = \frac{1}{2}\,\frac{V_S^2}{R\,(1+Q^2)} \implies \text{as if } V_S \text{ is delvering power to a resistor }R(1+Q^2)$$

Now this is interesting. Think about it. It says if you were to apply the whole voltage V_{s} across the resistor, the resistor would need to go up by 1+Q^{2} to keep the power same. If you don’t increase the resistor, the power drop across resistor would be huge because it sees the whole V_{S} now instead of small V_{R} as it saw in series case. This is why a series resistor gets a boosting factor of 1+Q^{2} in its parallel equivalent counterpart.

Physically it means voltage across R increased by factor Q. Remember in a series RL circuit, if a resistor has V_{R} voltage, the inductor would have QV_{R} voltage. Now when you move this resistor in parallel to inductor, resistor also taps a bigger voltage QV_{R}. So if voltage goes up by Q, power goes by up Q^{2}, therefore R also has to go up by Q^{2} to keep overall power same. Or you can say if voltage goes up by Q, current has to go down by Q to keep the power same (just like a transformer where if voltage goes up by turn ratio N, current goes down by N). So ratio \(\frac{QV}{\frac{I}{Q}}\) gives you \(Q^2\frac{V}{I}\) i.e., Q^{2} times higher impedance. Ok wait, you just said that it gets boosted by 1+Q^{2}, and now you say Q^{2}. Where did 1 go? To give you intuition behind boosting (i.e., resistor tapping a bigger voltage now), we said this bigger voltage is QV_{R} but it is actually V_{S} and that is almost equal to QV_{R} for Q>>1 as revealed by Eq. (2). So, the factor 1 is there if you want to be very precise, but it wouldn’t be unfair to say Q is usually much greater than one, and to keep things simple (and memorable), we can just say impedance is boosted by Q^{2}.

Now that we argued that it makes sense for a series resistor to get boosted by factor Q^{2} when we place the resistor in parallel, you may ask why didn’t it happen to inductor because Eq. (1) tells us reactance stays almost same.

Let’s go back to series RL circuit. Inductor already had big voltage across it QV_{R}. Going from series to parallel did not get it much bigger of voltage boost. It was QV_{R} in series, and it is V_{S} now in parallel. And as stated before, QV_{R} is almost equal to V_{S} for Q>>1. Therefore inductor value only has to go up a little to keep reactive power same. If inductor also gets a boost of Q^{2}, it will draw huge reactive power, then we can’t say this parallel impedance is equal to series impedance because series inductor would have been drawing relatively small reactive power. And when Q is small, then yes boost in inductance is also visible. For Q>>1, you just don’t see much boost, so it is fair to say series and parallel reactance stays same.

Let’s run quick math to see this through. Reactive power across inductor in series RL circuit can be given as:

$$ Q = \frac{1}{2}\,\frac{(QV_R)^2}{X} $$
$$ Q = \frac{1}{2}\,\frac{Q^2V_S^2}{X\,(1+Q^2)} \;\;\; \text{because}\; V_R = \frac{V_S}{\sqrt{1+Q^2}}$$
$$ Q = \frac{1}{2}\,\frac{V_S^2}{X\,(1+\frac{1}{Q^2})}\implies \text{as if } V_S \text{ is delvering reactive power to a reactance }X\left(1+\frac{1}{Q^2}\right)$$

Note that a common misconception that exists is that this series to parallel impedance transformation is narrowband. The transformation itself is not narrow band, it is Q. Quality factor changes over frequency, and you need to update R and X values based on frequency. If you can do that, it is as wideband as you want. But you won’t be able to do that. Your typical case of use would be: you figured out what is parallel equivalent of your series circuit at one frequency, you went ahead and replaced that series circuit with parallel one. So that’s that. At that frequency, your series and parallel circuit would behave exactly same, at frequencies nearby their response would still be similar because Q wouldn’t have changed much, but once you start looking at far off frequencies, all bets are off because Q would have changed a lot.

RFInsights

Published: 18 Feb 2023

Last Edit: 18 Feb 2023

The post Series to Parallel Conversion – Intuition appeared first on RFIC Design.

]]>