Power Amplifiers (PA) are in the transmitting chain of a wireless system. They are the final amplification stage before the signal is transmitted, and therefore must produce enough output power to overcome channel losses between the transmitter and the receiver. In this tutorial, we are going to have a detailed look at mm-wave PA design.
The first step in designing a PA is topology selection. Let’s look at the standard amplifying blocks shown in image below. We have common emitter (CE). It has high input impedance and high output impedance which is great. Reverse isolation is poor because there is miller capacitance between collector and base. And also the output power is limited by the collector emitter breakdown voltage, BVCEO.
The next candidate then is common base amplifier (CB). Common base voltage swing would appear across collector and base. CB can produce higher output power as it we can put higher voltage swings voltage across it compared to CE (BVCBO > BVCEO). But, the input impedance is very low, making it very difficult to drive.
Next we have cascode, which has properties of both common base and common emitter. Upper transistor works as common base, generating higher output power. Lower transistor is common emitter, providing higher input impedance. Also there is no direct feedback capacitor from output to input, thus reverse isolation is also very good. It makes sense to go for cascode, so go the most of mm-wave PA designs.
PAs are designed using loadpull simulations because:
Here’s how to launch Loadpull workbench in Keysight ADS software, as shown in image below.
We have chosen cascode as our core amplifier and connected it to the load pull instrument as shown in image below. Our goal was 10dbm. Let’s do 13dBm in order to accommodate losses (3dB higher? let it be, this is 94GHz you are talking about).
We are going to run multiple load pull simulations to optimize device size, bias, and supply voltage:
Run loadpull simulation. Start with approximate bias settings, input power, device size etc. and tune them as you optimize loadpull impedance. We start with 0.8V VBE of input transistor, 1.8V at cascode base and 4V VCC. Please read plots below from left to right. These are loadpull iterations we did. We highlight in yellow color what we changed in each simulation.
Insert the loadpull impedance (center point of converged contours shown in bottom right image above) in sourcepull setup and run sim.
Run loadpull. Use loadpull impedance and Run sourcepull. Use sourcepull impedance and run loadpull. Repeat this a couple times until you have converged to a loadpull and a sourcepull impedance.
We got following:
Comment: We don’t need to overdrive the PA, so Pavs has been decreased. Alright, we are done with loadpull of mm-wave pa.
We biased in class AB which would typically have efficiencies around 50-60%. This is true for low frequencies where parasitics can be ignored and design follows the simple math. But at 94GHz even the fF of capacitors matter! And they make voltage and current waveforms overlapping, so there is power dissipation across the device which degrades the efficiency.
Terminate the PA with load and source impedances found above and do harmonic balance analysis with power sweep. Setup is shown in image below.
Results are very close to loadpull simulations but not exactly the same. Why? Because harmonic impedances are not open-circuited in this case. We observe our peak PAE
Before we proceed, let’s just see for the sake of our understanding, the difference between small and large signal impedance. Run an s-param simulation and compare how does it look against source and loadpull impedances. We found that sourcepull impedance was very close to S11 but loadpull was very different than S22. It makes sense because the output experiences large voltage swings, and hence its large signal impedance is different than small signal s-param impedance.
You clearly see in image below that if you were to proceed with small signal matching of your PA, your Pout and PAE would have been crap.
Four possibilities using L-match. Choose the one which suits your needs.
We have chosen the first one with shunt inductor and series capacitor. We will bias out collector through shunt inductor and use this capacitor as DC block for output. Hence, this network serves as a matching network as well as bias T for mm-wave pa.
We are on track. Pout and PAE after matching match loadpull simulations.
We added Q to inductors. Two things happened. First because of the loss at output inductor, our Psat has decreased by 0.5dBm and our PAE has decreased by 12%. Second, the gain saw a big reduction because it takes into account both input and output losses. Now, our peak PAE is not at -5dBm but -2dBm.
Replace ideal voltage sources with realistic models:
Adding wirebond inductances and bypass caps didn’t impact Pout or PAE. Phew. Let’s move on.
Use s-param simulations and StabFact in ADS. Note that there is ever going debate on what is the correct test for stability as some folks do not like small-signal stability tests on devices which operate in large signal. You should do your due diligence to run different tests for stability after you are done with design (like run a transient sim, no one would argue on that). However, to progress through design optimization stages, we think k-factor or mu are good enough. So, let’s run k-factor (StabFact in ADS) and see what happens.
Add a series resistor at base to stabilize source and make sure bypass cap is sufficient for low frequencies.
Although PA is stable now, add a de-qued capacitor at VCC node just as a precaution (because we know this node has tendency to get unstable)
Upper base node is highly prone to oscillation in mm-wave power amplifiers. Even a little parasitic inductor (~5pH) can make PA oscillate. Add a parasitic inductor, and see what happens:
The only way forward here is to reduce parasitic inductance as much as possible or introduce loss. We show that adding \(5\,\Omega\) resistance solves the issue (StabFact > 1)
We are going to use a process which has 5 thin metal layers (M1-M5) for general purpose routings, 2 thick top layers (TM1-TM2) used for RF routing, MIM capacitors and Rsil Rppd resistors. This is how a transistor looks in our PDK:
Make a floor plan of where do you want things to be. We start with upperbase connection before anything else since we know this node needs the lowest inductance possible for stability of mm-wave cascode.
You can use whatever EM software you have available. We had Sonnet. In the image below, we show routing from the base node of cascode to the top metal layer. In Sonnet, your structure is enclosed in a closed metal box which serves as a ground reference. “BoxWall” is a port which connects between this metal box and your feedline and then you de-embed your feedline (it’s similar to Waveport in HFSS software). Read more on Sonnet in  &  if you are interested.
Worth mentioning that a common misconception about de-embedding: it completely de-embeds feed line. Not correct. Fringing fields are not de-embedded as shown in image below .
Export s-param model from EM sim. Attach it to your schematic, and run HB and s-param sim. We see that k-factor is greater than 1 showing that it is unconditionally stable. We did a good job in minimizing the inductance of this connection.
Connection from transistor collector on M1 to layer to topmost layer (TM2).
Insert exported s-param in schematic and run sim. Results look great. Very little drop in Pout and PAE.
Add matching network capacitor in EM sim
Insert exported s-param model in schematic and simulate.
We are doing this step by step to keep track of where do we lose performance. Losing 1% PAE or 0.2 dB of power is not a big deal, it maybe because matching is not EM optimized yet. Keep on adding more stuff and optimize it later altogether (optimize in small groups if things get out of control).
We added output matching inductor. Let’s run the sim.
Results look great. At this point, simulate all the EMs together (base connection, output cap and ind). Optimize and re-simulate. Few iterations and you should be close (however, we should mention this process of optimization is very tiring and you don’t actually do “few”, you do a lot EM sim, optimize, EM sim, optimize…it’s frustrating. Don’t worry, AI is coming to help, and beside in Industry you don’t need to do this, they have hired folks to do these optimization for you)
Here is how our optimized layout for upperbase connection and output matching looked like. We did not do input matching. Give us a break. We think you got a pretty good idea what’s the process like. This completes our design of mm-wave PA.
These are the final results. Just for fun, we compare with ideal components vs layout. We see 1dB loss in Pout, 14% drop in PAE and about 3dB drop in gain. Also interesting to note that s-param look quite the same. At this point, you have one design ready and you know what to expect from a 94GHz PA. Now is the time for you to get creative and start thinking of matching networks other than L-section to reduce the loss. There is an optimum for matching network order that give you the lowest insertion loss. Yes, lower number of elements are not always lowest in loss. Intuitively adding sections can decrease the insertion loss since it also lowers the network Q factor. Adding too many sections, though, can counterbalance this benefit. Check last two slides of Niknejad.
We taped out a PA designed at 28GHz using above steps. Image below shows chip photo.
This is how it looked like in measurement:
We hope you enjoyed our mm-wave PA design tutorial. Please leave us a feedback if you find typos or mistakes.
Equations for Harmonic Balance Plots:
Date Published: 29 Dec 2022
Last Edit: 02 Feb 2023