RFIC Design


RFIC Debug Stories

Debugs are hard! We often spend more time in debugging than designing a chip. You tapeout a chip, measure it, and see some functional or performance issues. You start debugging it, figuring out the origins of problem and improve it in the next tapeout. You document it well only to realize it later that nobody is going to read it. It gets lost in myriad of documents at worst, or stays within your tiny workplace circle at best. There is a great deal of learning that unlocks with debugs. With RFIC Debug Stories, we intend to present this learning to you in hope that it saves you from weeks or months of debug effort and you don’t go reinventing the wheel yourself. Even if it saves you a day to spend more time with your family and friends, mission accomplished.